`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/10 17:56:25
// Design Name: 
// Module Name: Complent_4bit_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Complent_4bit_tb(

);
    reg[3:0] A_tb;
    wire[3:0] Y_tb;
    
    integer a,b;
    initial
    begin
        for (a = 0; a < 16; a = a + 1)
        begin
            A_tb = a;
            #100;
        end
    end
    
    Complent_4bit_TOP complent_4bit_TOP_tb(
        .A(A_tb),
        .Y(Y_tb)
    );
    
endmodule
